1. Field
Embodiments of the invention relate to a memory device.
2. Description of the Related Art
A memory cell of a memory device includes a transistor functioning as a switch and a capacitor storing charges (or data). “High” (logic 1) or “low” (logic 0) of data is determined depending on whether a charge is present in the capacitor of a memory cell, that is, depending on whether a voltage at the terminal of the capacitor is high or low.
The retention of data basically has no consumption of power because the data is retained in such a manner that charges have been accumulated in the capacitor. However, data may be lost because the amount of charges initially stored in the capacitor becomes extinct in the leakage current attributable to the PN junction of an MOS transistor. In order to prevent such a problem, data within a memory cell needs to be read before the data is lost, and the normal amount of charges needs to be recharged based on the read information. When such an operation is periodically repeated, the memory of data is retained. Such a recharging process of cell charges is called a refresh operation.
Data stored in memory cells may be damaged because the electrons of the cell capacitors included in the memory cells coupled to the adjacent word lines are introduced/drained by electromagnetic waves generated when the word line is toggled in the active state and the precharge state.